This application is based on Japanese Patent Application No. 2001-367068, filed on Nov. 30, 2001, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device whose equivalent circuit has a load resistor connected to an impurity diffusion region formed in the surface layer of a semiconductor substrate, and its manufacture method.
B) Description of the Related Art
Polysilicon of high resistance has been used as a load resistor element of a static random access memory (SRAM) whose cell is constituted of four metal/oxide/semiconductor type field effect transistors (MOSFETs) and two load resistor elements. Load resistor elements of polysilicon increase a cell area. A load resistor cell of polysilicon is required to be connected to an upper level wiring layer, the manufacture processes become complicated.
Japanese Patent Laid-open Publication No. 53-68991 discloses a semiconductor device in which leak current flowing through a pn junction between a source or drain region and a well of a MOSFET constituting a memory cell is used as current flowing through a load resistor element. This method requires no load resistor element so that a cell area can be reduced.
Data retention technique by utilizing off-leak current of a PMOSFET used as a transfer transistor of an SRAM is disclosed in xe2x80x9cA 1.9-xcexcm2 Loadless CMOS Four-Transistor SRAM Cell in a 0.18-xcexcm Logic Technologyxe2x80x9d, Noda et al (Paper made public on IEDM, 1998).
The invention disclosed in JP-A-53-68991 does not require a dedicated area for forming a load resistor element. However, in order to obtain leak current having a desired quantity, it is necessary to increase the area of a pn junction and apply a necessary back bias to the well. Micro fine patterns and low voltage of recent semiconductor integrated circuit devices flow only a small leak current through a pn junction. It is therefore difficult to retain leak current having a desired quantity.
With the method of utilizing off-leak current of a transfer transistor of an SRAM, as gate leak current increases because of a thinned gate insulating film, it becomes necessary to increase off-current of a transfer transistor. As the off-leak current of the transfer transistor increases, there is a large danger that when data is written, this data is written also in a cell not selected. This destroys the data.
An object of this invention is to provide a semiconductor device having a small cell area and a high stability of operation.
Another object of the invention is to provide a method of manufacturing such a semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first well of a first conductivity type formed in a partial region of a surface layer of a semiconductor substrate; a MOS transistor having a gate insulating film formed on a partial area of a surface of the first well, a gate electrode disposed on the gate insulating film and first and second impurity diffusion regions of a second conductivity type opposite to the first conductivity type formed in a surface layer of the first well on both sides of the gate electrode; and a high leak current structure which makes a leak current density when a reverse bias voltage is applied across the first impurity diffusion region of the MOS transistor and the first well become higher than a leak current density when the same reverse bias voltage is applied across the second impurity diffusion region and the first well.
The high leak current structure can supply current to the first impurity diffusion region. Since it is unnecessary to prepare an area for disposing a resistor element for current supply, high integration of a semiconductor device is possible.
According to another aspect of the present invention, there is provided a semiconductor device comprising: an element separation insulating film formed in a partial region of a surface layer of a semiconductor substrate and defining an outer periphery of each of first and second active regions; an impurity diffusion region formed in a surface layer of the first active region; a first connection member consisting of conductive material and extending from a position above the second active region to a position above the element separation insulating film adjacent to the first active region; an interlayer insulating film covering the impurity diffusion region and the first connection member; a via hole formed through the interlayer insulating film, the via hole overlapping a partial area of the impurity diffusion region and a partial area of the first connection member as viewed along a direction in parallel to a normal to a surface of the semiconductor substrate; a second connection member buried in a space in the via hole adjacent to the semiconductor substrate, the second connection member electrically connecting the impurity diffusion region and the first connection member; a third connection member buried in a space in the via hole on the opposite side to the semiconductor substrate, the third connection member having a resistivity higher than a resistivity of the second connection member; and a wiring formed on the interlayer insulating film and connected to the third connection member.
Current is supplied to the impurity diffusion region from the wiring line via the third and second connection members. Since the third connection member functions as the resistor element, it is unnecessary to prepare a dedicated area for the resistor element. High integration of a semiconductor device is therefore possible. The first connection member is connected to the impurity diffusion region via the second connection member. Since the second connection member has a low resistance, the resistance between the first connection member and impurity diffusion region can be maintained low.
According to another aspect of the present invention, there is provided a semiconductor device comprising: an element separation insulating film formed in a partial region of a surface layer of a semiconductor substrate and defining an outer periphery of each of first and second active regions; an impurity diffusion region formed in a surface layer of the first active region; a first connection member consisting of conductive material, the first connection member extending from a position above the second active region to a position above the first active region via a region on the element separation insulating film; a conductive film electrically interconnecting the first connection member and the impurity diffusion region, the conductive film extending from an upper surface of the first connection member to an upper surface of the impurity diffusion region via a side wall of the first connection member; an interlayer insulating film covering the impurity diffusion region and the first connection member; a via hole formed through the interlayer insulating film, the via hole overlapping a partial area of the conductive film as viewed along a direction in parallel to a normal to a surface of the semiconductor substrate; a second connection member buried in the via hole and consisting of material having a resistivity higher than a resistivity of the conductive film; and a wiring formed on the interlayer insulating film and connected to the second connection member.
Current is supplied to the impurity diffusion region from the second connection member. Since the second connection member functions as the resistor element, it is unnecessary to prepare a dedicated area for the resistor element. High integration of a semiconductor device is therefore possible. The first connection member is connected to the impurity diffusion region via the conductive film. Therefore, even if the second connection member has a high resistance, the resistance between the first connection member and impurity diffusion region can be maintained low.
As above, current can be supplied to the impurity diffusion region formed in the surface layer of a semiconductor substrate from the power supply wiring line via the resistance member without reserving a dedicated area for a resistor element. By applying this structure to an SRAM, current necessary for data retention can be obtained without increasing the cell area.